Short channel transistors are suitable for several different applications, such as complementary metal-oxide semiconductor (CMOS) devices. However, leakage current when a short channel transistor is in the off-state may be unacceptable for some applications. For example, low-leakage transistors may be desirable for applications such as analog/RF, EDRAM, or the like. Additionally, in some applications, both short-channel devices and long-channel devices are needed on the same semiconductor chip. However, the top down footprint of both transistor types are not able to be fabricated with a single process flow. For example, when an analog/RF transistor is needed on the same chip as a CMOS device, the analog/RF transistors need to be stacked together to reduce the total leakage. The stacking required for the analog/RF transistors produces a larger top down footprint than the footprint needed for CMOS transistors. Additionally, when the leakage requirements are exceptionally low (e.g., DRAM and EDRAM) the transistors cannot be fabricated on the same chip unless additional lithography operations are included in the processing. These additional processes operations greatly increase the cost of the chip and reduce throughput.
Thus, improvements are needed in the formation of long-channel and short-channel transistors on the same semiconductor chip.